A typical flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate.
The cells are usually grouped into sections called "erase blocks." Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, where all floating gate memory cells in the erase block are erased in a single operation.
One term frequently used to categorize "lifetime" is P/E. P/E refers to a Program/Erase cycle, when data is written to a cell, erased, and re-written. Different types of flash have differing lifetimes, or limits to the number of P/E cycles supported before the cell fails.
P/E cycle limitations are inherent to flash, and refer to program/erase cycle maximum numbers before information is not readable or writeable. This is the primary flash limitation. As with any memory, various semiconductor characteristics, fab density, and controller determine P/E lifetime, speed, cost, and transfer rates.
MLC vs. eMLC vs. SLC vs. TLC
There are four types of NAND flash, differing in number of P/E cycles per lifetime, and defined by their construction:
- SLC -- Single Level Cell: the most expensive, longest lived (high P/E), and generally fastest. Bits are stored only as 2 voltage levels, or a "1" or "0." In SLC less data is stored per cell, so the per unit storage cost is higher.
- MLC -- Multi-Level Cell: is consumer grade and used in phones, cameras, and USB sticks. The stored charge in MLC may be interpreted as a variety of values, 0 to 3, or 4 possible states, and may store 2 bits. With shorter lifetimes, usually 10x less than SLC, the advantage of this memory is that the cost is 2- 4x less than SLC, but with lower write speeds. MLC typically uses some form of error correction code per block.
- eMLC -- Enterprise (grade) Multi-Level Cell: is MLC with longer life, usually because of an advanced controller operating the cell and error recovery techniques, construction density, or some combination of the two. Violin has an interesting explanation of the practical differences between NAND types here.
- TLC -- Triple Level Cell: championed by Samsung, TLC has higher power and error correction requirements, and higher wear levels. TLC is targeted at environments with predominant read uses, and has not been commonly used.
NOR vs. NAND Architectures
The memory cells of both an EEPROM (electrically erasable programmable read-only memory) memory array and a flash memory array are typically arranged into either a "NOR" or "NAND" architecture:
- NOR architecture -- each cell directly coupled to a bit line, allows true random access.
- NAND architecture -- cells coupled into "strings" of cells, such that each cell is coupled indirectly to a bit line and requires activating the other cells of the string for access.
Flash memory is a type of EEPROM, but the term EEPROM usually refers to non-flash EEPROM, where data can be erased in small units, usually bytes. Most solid-state drives, USB flash, and memory cards use NAND flash. Erasing, usually a slow process, is much faster in flash than non-flash EEPROM, because of the large block sizes used in flash.
For a perspective of storage speeds, the hierarchy from fastest to slowest storage memory types is:
DRAM > NAND flash > Spinning Disk > Tape
NAND is about 1000x faster than spinning disks, but DRAM is 1000x faster than NAND. NAND is about 10x less expensive than DRAM, but more expensive than spinning disks.