HGST Adds PCIe SSD Family; New Architecture Hits 3M IOPS
HGST introduced this week its new FlashMAX III family of PCI Express (PCIe) accelerators, that are built from the ground up for extreme application performance. This new family will be made available in Q3 2014, and is currently being qualified by select OEMs.
According to the specifications, the FlashMAX III family includes three models/capacities: 1100 GB, 1650 GB, and 2200 GB. They will also provide up to 549,000 Random Read IOPS (4K) and up to 200,000 Mixed Sustained Random IOPS (70:30 R:W). The FlashMAX III trio will even support PCIe 3.0, which is currently used in today's server platforms. Read: Building a Business Case for Flash Storage
The company also revealed its new HGST ServerCache software that allows IT administrators to inject acceleration into their existing storage infrastructure. This software is capable of creating an SSD cache of the most frequently used data. ServerCache will also run on any server application hosted on a Windows Server-based or Linux-based SAN or DAS.
"HGST's new FlashMAX III PCIe SSD and ServerCache software are suited for performance-intensive applications including databases, SQL servers, data warehouses, big data deployment and video post-production applications," HGST's announcement stated. "Each address distinct needs for flash storage solutions based on performance, capacity, cost and deployment time requirements."
HGST's ServerCache software is available now for a free 30-day trial. The cost is $995 per physical server.
In addition to the FlashMAX III family and ServerCache software, the company recently previewed a new architecture for SSDs at the Flash Memory Summit. This architecture allows SSDs to achieve a performance level that can only be reached by using HGST's new, latency-optimized interface protocols and next-generation non-volatile memory components.
According to HGST, the SSD managed 3 million random read IOPS of 512 Bytes each when operating in a queued environment. With non-queued settings, the SSD delivered a random read access latency of 1.5 microseconds (us). HGST indicates that these achievements cannot be made when using existing NAND Flash memories and SSD architectures.
HGST's announcement said that the memory used in the SSD includes 45 nm Phase Change Memory components with a 1 Gb capacity. Also included was a low-latency interface architecture that’s not only optimized for performance, but "agnostic" to the specific underlying memory technology. By using its controller know-how, HGST managed to integrate 1 Gb PCM chips to build a full-height prototype.
"Three million IOPs is exceptional, but that is not the most exciting part of the demonstration," said Dr. Zvonimir Bandic, manager of Storage Architecture at HGST Research. "What is really exciting is to be able to deliver latencies close to 1us for small block random reads. This is something that just cannot be done with NAND Flash and current controller and interface technologies."
HGST's PCM SSD will be demonstrated at the 2014 Flash Memory Summit in the Santa Clara Convention Center, Santa Clara, CA on Wednesday and Thursday in Booth #316.