IBM Discusses Power7+ Microprocessor Details

IBM has unveiled some details about its next-generation Power processor. Still called "Power7+", IBM said that the updated architecture will integrate eight cores and support four threads per core.

The 32 nm SOI processor will have a die size of 567 mm2 and carry 2.1 billion transistors. Each core will get 256 KB L2 cache and 80 MB eDRAM as L3 cache will be shared among all cores. The architecture can be scaled to 32 sockets per system, delivering up to 256 cores and 1,024 threads per system.

IBM did not specify the anticipated clock speed, but noted that the core supports 25 more clock speed than the current Power7, which tops out at 4.25 GHz. At least in theory, the Power7+ could be clocked at about 5.3 GHz.

The first Power processor, developed for the RS/6000 PowerServers and PowerStation workstations, was released in 1990 with a clocks peed of up to 30 MHz. The CPU was manufactured in a 1,000 nm process and had 6.9 million transistors. The current 8-core Power7 CPU was launched in February 2010 and is built in 45 nm.

Wolfgang Gruener is a contributor to Tom's IT Pro. He is currently principal analyst at Ndicio Research, a market analysis firm that focuses on cloud computing and disruptive technologies, and maintains the conceivablytech.com blog. An 18-year veteran in IT journalism and market research, he previously published TG Daily and was managing editor of Tom's Hardware news, which he grew from a link collection in the early 2000s into one of the most comprehensive and trusted technology news sources.

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